Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, processors, and so forth).
The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Programmable lookup tables are often included in PLDs. A lookup table is a circuit that provides an output value selected from among two or more stored values in response to a combination of input values. One method of implementing a lookup table (LUT) is to store 2**n values in memory cells (e.g., configuration memory cells in an FPGA), where n is the number of input signals to the LUT. Each of the n input signals is then utilized to select only half of the remaining stored values. For example, a 4-input LUT can utilize the four input signals to select first eight, then four, then two, and finally one of 16 stored values.
FIG. 1 illustrates a well-known LUT circuit that functions according to this well-known method. A 2-input LUT is shown, as in many of the drawings herein, to clarify the drawings. Many LUTs now included in FPGAs, for example, utilize four input signals. The illustrated examples are easily modified to accommodate four input signals (or other numbers of input signals) by one of skill in the relevant arts.
The LUT circuit of FIG. 1 has two input signals IN1 and IN2, and can provide at the output terminal OUT any of four values stored in memory cells MC-0 through MC-3. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The LUT circuit includes six inverters 101–106, six N-channel transistors 111–116, and a pullup 121 implemented using a P-channel transistor. N-channel transistors 111–116 implement a well-known 4-to-1 multiplexer circuit.
Inverters 105–106 and pullup 121 implement a well-known output buffer. The output (node M) of the multiplexer circuit drives inverter 105 and is pulled to power high (VDD) by P-channel transistor 121. The output terminal of inverter 105 is coupled to the gate terminal of pullup 121 and also drives inverter 106, which provides the output signal OUT to the output terminal. Pullup 121 serves to pull node M fully to power high VDD when a memory cell storing a high value is selected by transistors 111–116.
The LUT circuit of FIG. 1 functions as shown in the example illustrated in FIG. 2, wherein both input signals IN1 and IN2 are high, memory cells MC-0 through MC-2 store low values, and memory cell MC-3 stores a high value. When input signal IN2 is high, the output of inverter 101 goes low, turning off transistors 112 and 114. The output of inverter 101 also drives inverter 103, so the output of inverter 103 goes high, turning on transistors 111 and 113. Similarly, when input signal IN1 is high, the output of inverter 102 goes low, turning off transistor 116. The output of inverter 102 also drives inverter 104, so the output of inverter 104 goes high, turning on transistor 115. Thus, a path is enabled between memory cell MC-3 and node M, and the high value stored in memory cell MC-3 is provided to node M and hence to output terminal OUT. A heavy line in FIG. 2 shows the signal path now enabled between memory cell MC-3 and output terminal OUT.
Another well-known LUT circuit (not shown) is similar to that of FIG. 1. N-channel transistors 111–116 are replaced by CMOS passgates, which include N-channel and P-channel transistors coupled in parallel. The N-channel transistors are coupled as shown in FIG. 1. Each P-channel transistor is gated by the complementary signal to the signal driving the associated N-channel transistor. In this version of the circuit pullup 121 can be omitted, because the P-channel transistors in the CMOS passgates ensure a fully high value on node M.
A PLD can include hundreds of thousands of LUTs implementing large amounts of user logic. In some designs, several LUTs are preferably included on each path between two clocked elements. Hence, the delay through each LUT can be quite significant in determining the speed at which a user design will operate. Therefore, it is desirable to provide a LUT circuit having a reduced delay when compared to known LUT circuits.